1. Field of the System
The present system relates to field programmable gate array (FPGA) devices. More specifically, the system relates to a multi-level routing architecture having transmitters and receivers between logic modules in an FPGA that will increase the performance in the FPGA.
2. Background
FPGAs are known in the art. An FPGA comprises any number of logic modules, an interconnect routing architecture and programmable elements that may be programmed to selectively interconnect the logic modules to one another and to define the functions of the logic modules. An FPGA is an array of uncommitted gates with uncommitted wiring channels. To implement a particular circuit function, the circuit is mapped into an array and the wiring channels' appropriate connections are programmed to implement the necessary wiring connections that form the user circuit.
An FPGA circuit can be programmed to implement virtually any set of functions. Input signals are processed by the programmed circuit to produce the desired set of outputs. Such inputs flow from a user's system, through input buffers and through the circuit, and finally back out the user's system via output buffers. Such buffers provide any or all of the following input/output (I/O) functions: voltage gain, current gain, level translation, delay, signal isolation or hysteresis.
An FPGA core tile may be employed as a stand-alone FPGA, repeated in a rectangular array of core tiles, or included with other devices in a system-on-a-chip (SOC). The core FPGA tile may include an array of logic modules, and input/output modules. An FPGA core tile may also include other components such as read only memory (ROM) modules. Horizontal and vertical routing channels provide interconnections between the various components within an FPGA core tile. Programmable connections are provided by programmable elements between the routing resources.
The programmable elements in an FPGA can be either one-time programmable or re-programmable. Re-programmable elements used in FPGA technologies may comprise transistors or other re-programmable elements as is well known to those of ordinary skill in the art. One-time programmable elements used in FPGA technologies may comprise antifuse devices.
The interconnect routing architecture in a large FPGA that has long tracks may be cumbersome and slow due to the length of the tracks and the capacitive load of all the unprogrammed programmable elements on the tracks. The delay on the track is proportional to the square of the track length.
One method that has been used to circumvent the excessive track length problem is to insert repeaters (bi-directional buffers) at interim distances on the long-distance track. However, each of the repeaters needs at least two additional direction control signals that have to be selectively programmed to conform with the assigned net. The additional control signals add to the area, and therefore the cost, of the device and the complexity of the routing software.
Another method used to circumvent the excessive track length problem is to depopulate the tracks by reducing the number of programmable elements. This reduces the capacitive loading, (fewer programmable elements) and also reduces the connectivity of these tracks. However, this also reduces the flexibility of routing solutions and increases the chance of design failures.
Yet another method used to circumvent the excessive track length problem is to create a hierarchical routing architecture. In a hierarchical routing architecture, a signal has to transfer “up” the hierarchy, travel the distance, and then transfer “down” the hierarchy to reach its destination. In these types of architectures there are signal bottlenecks in the transfer-up points and the transfer-down points. It costs too much in terms of area on the die to provide full access between all lowest level resources and all the higher-level resources. The problem is usually managed by either providing very sparse access across hierarchies or introducing intermediate levels of hierarchy. Both solutions result in routing inflexibility and delay penalties.
Hence, there is a need in the art for a multi-level hierarchical routing architecture that provides full access between the lower-level resources and the higher-level resources at almost no additional cost.